Tags: ADC, cmos, education, flash, sparkle codes, sparkles, theory, thermometer bubbles, thermometer code, two-step flash

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Abstract:

          “The Summary” section presents the architecture of the two-step flash ADC with its advantages and disadvantages listed. “The Story” section explains the two-step flash architecture. Architectures with and without the 2N/2 amplifier are analyzed. The two-step flash architecture is compared to the flash architecture. The implementation of subtractor and 2N/2 amplifier are presented. Advantages and disadvantages of the two-step flash architectures are analyzed.

 

THE SUMMARY

 

two-step flash adc - additional sample-and-hold

Figure 9: Two-step flash ADC.

 

Advantages:

  • the power and the area are greatly reduced compared to the standard flash ADC, especially for the big number of bits (see Table 2)

 

Remarks:

  • architecture:

    • two N/2-bit flash ADCs:

      • 2 x 2N/2 resistors

      • 2 x (2N/2 – 1) comparators

    • DAC circuit

    • subtractor

    • two non-overlapping clocks

    • buffers can be desired

  • sources of accuracy errors:

    • the same as in the flash ADC:

      • matching of resistors

      • offset voltage of comparators

    • subtractor and buffers – problems of an opamp like:

      • offset voltage

      • finite gain

      • bandwidth

      • stability

 

Disadvantages:

  • slower than the standard flash ADC

    • the conversion takes two steps instead of one as compared to the standard flash ADC

  • when using the architectures from Fig. 14 and 15, it may happen that all bits from 2nd flash ADC (ADC2) have wrong values (the problem is described in “The Story” below)

 

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THE STORY

 

          Fig. 10 presents the two-step flash ADC architecture called also the parallel feed-forward ADC. Input signal VIN is sampled by the sample-and-hold circuit. The sampled voltage V1 is processed by the first flash ADC (ADC1) and results in N/2 bits that are used by the DAC circuit. The difference between the sampled input signal V1 and the voltage from DAC V2 is handled by the second flash ADC (ADC2). In the end, N bits are received. Half bits from the ADC1 and the second half bits from ADC2.

          Small remark: during the sample phase, V1 voltage follows VIN voltage. ADC1 processes this V1 voltage and the proper values of first half of bits and V2 voltage can be achieved just at the beginning of the hold phase. ADC2 works also during the sample phase, but most often it processes wrong V3 value until V3 does not stabilize during the hold phase.

 

two-step flash adc

Figure 10: N-bit two-step flash ADC.

 

          ADC1 makes coarse conversion, while ADC2 makes fine conversion. Comparators in ADC1 compare V1 with full range of voltage (from the power supply to the ground). In ADC2, comparators must be able to recognize smaller differences between voltages. This is illustrated in Fig. 11.

 

two-step flash adc - conversion

Figure 11: Conversion of an analog signal into digital code in the 4-bit two-step flash ADC from Fig. 10. Power supply is equal to 4 V.

 

         In order to relax requirements of ADC2 comparators, V3 voltage can be amplified by 2N/2 as it is shown in Fig. 12. Now, the ADC2 can have exactly the same architecture as ADC1. The conversion of such two-step flash ADC is presented in Fig. 13.

 

two-step flash adc - amplifier

Figure 12: N-bit two-step flash ADC with an amplifier, which gain is equal to 2N/2.

 

two-step flash adc - conversion

Figure 13: Conversion of an analog signal into digital code in the two-step flash ADC from Fig. 12. Power supply is equal to 4 V.

 

         The advantage of the two-step flash ADC is the fact that this architecture is more power and area efficient than the standard flash ADC architecture. It is illustrated in Table 2.

 

Table 2: Number of resistors and comparators in the flash ADC and the two-step flash ADC architectures.

table - flash vs two-step flash

 

          One may wonder how is the subtractor and 2N/2 amplifier implemented. Functions of these two circuits can be fulfilled by one opamp with resistors around as it is shown in Fig. 14. The gain of the subtractor is the ratio of R2 to R1. Using the subtractor means that the sample-and-hold circuit and the DAC must be able to source/sink currents that flow through resistors. Buffers can be used to overcome this problem.

 

two-step flash adc - subtractor currents

Figure 14: Two-step flash ADC with a subtractor having the gain of R2/R1.

 

          One can also wonder why 4-bit two-step flash ADC uses two 2-bit flash ADCs and not for example one 3-bit flash ADC and one 1-bit flash ADC? Let’s analyze this, using 6-bit two-flash ADC. The reason why two 3-bit flash ADCs are used for 6-bit two-step flash ADC is the fact that the best approach for power and area requirements is when N-bit two-step flash ADC is implemented using two N/2-bit flash ADCs as it is presented in Table 3.

          One more remark: of course, odd-bit two-step flash ADCs can be constructed. However, in this case, the two flash ADCs have different number of bits. For example 2 bits + 1 bit or 1 bit + 2 bits. It means that ADC1 and ADC2 have different architectures and must be designed separately. That leads to spending more time on the project.

 

Table 3: The reason why the 6-bit two-step flash ADC consists of two 3-bit flash ADCs is the fact that this approach is most power and area efficient.

table - two-step bits for ADC1 and ADC2

 

          Here comes the big one. There is one big danger when using the two-step flash ADC architectures from Fig. 10 and 12. Analyze the following situation:

          Let’s use the architecture from Fig. 12 with the conversion of the analog signal shown in Fig. 13. Assume, that the input signal VIN changes from 3.750 V to 1.999 V. Do you see the problem?

          When VIN crosses 3.0 V, the output of comparator_3 (if you do not know where is the comparator_3, draw the 2-bit flash ADC architecture using Fig. 4 and Fig. 5) changes from “1” to “0”. What happens when VIN crosses 2.0 V and drops to 1.999 V? The output of comparator_2 should change from “1” to “0”? Yes, that’s true. Assuming that comparator_2 has no offset voltage. However, there is a bigger problem than the offset voltage. The problem is: after what time the output of comparator_2 will change from “1” to “0”? You can use ideal blocks and you will get ideal results immediately. No latency. In reality you face the real word. In silicon, electrons have finite speed. A comparator needs time to change its output from “1” to “0” or from “0” to “1”. This time depends on the gain of the comparator, the difference between its inputs and the load of comparator. This time can be 0.5 ns, 1 ns, 5 ns or 10 ns, and so on. But this time is finite not infinitely short.

          The problem exists when VIN is close to any value of voltage reference in ADC1 and sample and hold phases are short. As in the above example, when VIN voltage drops to 1.999 V just at the end of sample phase and the hold phase is equal to let’s say 5 ns, comparator_2 in ADC1 have only 5 ns to change its output from “1” to “0”. What’s more, the new ADC1 code must be processed by the DAC, substractor and ADC2!

          In order to analyze the above situation, that is when VIN changes its value from 3.750 V to 1.999 V, use Fig. 4, 5, 12 and 13. If a lot of words and longer text explanations make you a bit tired, look right now on Table 4. When VIN drops to 2.2 V, outputs of ADC1 comparators are equal to 011 and the ADC1 digital code is equal to 10. The reference voltage from DAC is equal to 2.00 V. The difference between VIN and the reference voltage from DAC is equal to 0.2 V. This value is amplified by 4, so the input of ADC2 is equal to 0.8 V. Outputs of ADC2 comparators are equal to 000 and the ADC2 digital code is equal to 00. When VIN drops to 1.999 V, ADC1 comparators should give 001 and the ADC1 digital code should be equal to 01. If the hold phase ends right after ADC1 digital output has changed from 10 to 01, ADC2 has no time to process new V3 – V2 difference. In this situation, the final digital code is 01 00 instead of 01 11. Thus all the bits from ADC2 are wrong! See Table 4 that illustrates the described situation.

          Shortly, the above situation can be presented as follows:

VIN changes:

2.200 V → 1.999 V

Corresponding digital code changes:

10 00 → 01 00 (temporary wrong code) → 01 11

 

Table 4: How the two-step flash ADC output digital code changes when VIN changes from 2.200 V to 1.999 V.

table - two-step flash analysis

 

          In order to solve this problem, see the architecture in Fig. 15. The sample-and-hold circuits (S/H) have been added. Clocks clk_1 and clk_2 are non-overlapping clocks. In the situation above (see Table 4), if sampled ADC1 digital code is equal to 10, ADC2 digital code will be 00, thus total output digital code is 10 00. On the other hand, if sampled ADC1 digital code is equal to 01, ADC2 digital code will be 11. As we see, the conversion error is equal to the one least significant bit (code 10 00 instead of 01 00). This a good result comparing to the two-step flash without the additional S/H circuits, where the obtained code may be 01 00 instead of 01 11 as presented in Table 4.

          The architecture in Fig. 15 is called a pipeline architecture.

 

two-step flash adc - additional sample-and-hold

Figure 15: Two-step flash ADC with additional sample-and-hold circuits creates a pipeline architecture.

 

Conclusion:

          Two-step flash ADC is the natural improvement of the flash ADC as the answer to improve resolution and decrease power consumption and occupied area. The cost of these improvements is reduced speed of conversion. The conversion takes two steps instead of one as in the case of the flash architecture. Thermometer bubbles may also be present as flash converters are implemented in two-step flash ADC. Additional sample-and-hold or track-and-hold circuits can be added to improve the reliability of the converter.

 

References:

  1. Baker R. Jacob, CMOS Circuit Design, Layout, and Simulation, 3rd Edition, 2010, John Wiley & Sons

  2. Camenzind H., Designing Analog Chips, February 2005

  3. Maloberti Franco, Data Converters, 2007, Springer

  4. Norsworthy S.R., Schreier R., Temes G.C., Delta-sigma Data Converters Theory, Design, and Simulation, 1997

  5. http://en.wikipedia.org/wiki/Delta-sigma_modulation

    Delta-sigma modulation (link available 2015.06)

  6. http://pdfserv.maximintegrated.com/en/an/AN634.pdf

    Maxim Integrated Products, Inc., TUTORIAL 634: Pipeline ADCs Come of Age, Nov 20, 2001 (link available 2015.06)

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    Maxim Integrated Products, Inc., TUTORIAL 810: UNDERSTANDING FLASH ADCS, (link available 2015.05)

  8. http://www.asdlib.org/onlineArticles/elabware/Scheeline_ADC/ADC_ADC.html#ADCMain

    Scheeline Alexander, Analog to Digital Conversion, (link available 2015.05)

  9. http://www.cypress.com/?id=4&rID=32117

    Document titled “Definitions of INL and DNL in an ADC” (link available 2015.05)

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  11. http://www.maximintegrated.com/en/app-notes/index.mvp/id/1023

    Maxim Integrated Products, Inc., TUTORIAL 1023: Understanding Pipelined ADCs (link available 2015.05)

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    Maxim Integrated Products, Inc., TUTORIAL 1870: Demystifying Delta-Sigma ADCs (link available 2015.06)