Tags: area, CMOS, reduction, speed, technology


New technology node means:

  • historically is introduced every 3 years

  • 70 % of feature sizes (main goal)

    • that leads to 50 % of area occupied by the circuit (width x length = 0.7 x 0.7 = 0.49)

  • 30 % faster (historically):

    • power supply reduced, gate oxide thickness reduced, current density Ion/W increased

      • smaller transistors and shorter interconnects = smaller capacitances = faster circuits





Area reduction for analog blocks

Area reduction for analog blocks is not as good as for digital parts when porting a design to new technology node. The main reasons are:

  • worse characteristics of transistors (for example: lower output Rds resistance, bigger leakage current)

  • lower supply voltages: lower signal swing, reduced voltage headroom


Area savings are obtained by architectural solutions.