Tags: ADC, analog-to-digital converter, cmos, education, integrating, single-slope, theory



     “The Summary” section presents the architecture of the single-slope integrating ADC with its advantages and disadvantages listed. “The Story” section explains the single-slope integrating architecture. The architecture is thoroughly analyzed. The advantages and disadvantages of the architecture are discussed.


integrating ADC - schematic

Figure 24: The single-slope integrating ADC.



  • resolution:

    • able to achieve 14 bits or higher [3, 7]

  • applications:

    • used in high-resolution applications [1, 3]

    • commonly found in slow-speed, low cost applications [1]

      • digital multi-meters

      • panel meters

      • voltage or current meters

      • monitoring DC signals in the instrumentation and industrial markets [7]

  • very inexpensive to produce [1]

  • low power consumption [3, 7]

  • very low offset and gain errors

  • highly linear

  • good noise performance [3]



  • the increase in number of bits doubles the conversion time [7]

  • the input signal value is converted into a number of clock pulses

  • competes with sigma-delta converters [7]

  • architecture:

    • sample-and-hold circuit

    • integrator

    • comparator

    • control logic block

    • counter

    • latches

  • sources of accuracy errors:

    • sample-and-hold circuit

    • negative reference voltage -VREF

    • resistor R1

    • capacitor C1

    • fclk_2

    • opamp:

      • offset voltage

      • bandwidth

      • finite gain

    • comparator:

      • offset voltage

      • latency



  • slow conversion [1, 3, 7]

    • typically less than a few hundred samples per second

  • sensitive (direct dependence of the digital output) to the values of:

    • resistor R1

    • capacitor C1

    • negative reference voltage -VREF




The schematic of the single-slope integrating ADC, is presented in Fig. 25. The single-slope integrating ADC consists of a sample-and-hold circuit, an integrator, a comparator, a control logic, a counter and latches.

integrating ADC - schematic

Figure 25: The single-slope integrating ADC.


     Notice, that VIN is positive and -VREF is negative. To convert positive voltages, a negative reference is needed. For negative input voltages, a positive referenced is needed.

     During the sample phase, the input signal VIN is sampled by the sample-and-hold circuit. “Reset” signal is high, thus the counter block is set to 0 and the switch S1 is closed, hence the voltage across the capacitor C1 is equal to 0 V. The comparator output voltage Vcomparator is high.

     When the hold phase begins, “reset” signal is set low. As a result, the counter starts counting clk_2 clock pulses, switch S1 is opened and the integrator begins to work. I1 current, that charges capacitor C1, is equal to:

5. eq. 1

     The integrator output voltage V1 rises linearly and follows the equation:

5. eq. 2

     The integrator output voltage V1 rises until it reaches Vsampled value. Hence the conversion time tc is equal to:

5. eq. 3

     It is worth to notice, that the conversion time tc depends on the sampled input signal value Vsampled. The higher the sampled voltage Vsampled, the longer the conversion time. See Fig. 26.

integrating ADC - conversions

Figure 26: Plot of V1 voltage in the single-slope integrating ADC – example of conversions.


     When the integrator output voltage V1 reaches Vsampled value, the comparator output voltage Vcomparator goes low. This is the signal for the control logic block to latch outputs of the counter and then set the “reset” signal high. Again, the counter is set to zero and the voltage across capacitor C1 is equal to 0 V. The sample-and-hold circuit is able to sample the next input voltage value and the ADC is ready to process the sampled value. The result of the conversion, N-bit output digital word bN-1bN-2…b1b0 can be read from the outputs of latches.

     During the conversion time tc, the counter counts clk_2 clock pulses. The number of clk_2 clock pulses is directly proportional to the Vsampled value. The number of clk_2 clock pulses is the final result of the conversion. For that reason, the clk_2 clock frequency must be many times faster than the bandwidth of the input signal.

     The maximum value of N-bit counter is the N-bit chain of ones, that is, 11…11. Its corresponding value in the decimal system is equal to 2N – 1. The counter can count 2N – 1 clk_2 clock pulses maximally. As a result, the maximum conversion time is equal to:


5. eq. 4


     Consequently, the minimum conversion frequency is equal to:

5. eq. 5


     The minimum conversion frequency fc_min should be at least two times greater than the frequency of the input signal (Nyquist’s sampling theorem). For example, when the input signal frequency is equal to 10 kHz, fc_min should be equal to 20 kHz. That means that tc_max should be equal to:

5. eq. 6

     If 10-bit single-slope integrating ADC is going to be constructed, that means that clk_2 clock period should be equal to:

5. eq. 7

     Thus, the clk_2 clock frequency in 10-bit single-slope integrating ADC for 10 kHz input signal should be equal to:

5. eq. 8

     If we exchange VIN and VREF connections, we can use the biggest advantage of the integrating converter – its ability to average the input signal due to the fact that the input voltage is applied to the integrator. This attribute is used in applications where the input signal is distorted by a noise. The noise averages and the voltage level of an input signal can be measured.


integrating ADC - average noise

Figure 27: Plot of V1 voltage in the single-slope integrating ADC – example of conversions.


     The biggest disadvantage of the single-slope architecture is the fact that the conversion time depends on values of capacitor C1, resistor R1 and the value of negative voltage reference -VREF – see Eq. 1 . In integrated circuits, the values of the designed capacitor or resistor can change typically as +/- 20%. But there is a solution to this problem. The enhanced architecture is called the dual-slope integrating ADC.



     The single-slope ADC architecture has the advantage to average noise of the input signal. Moreover, it achieves high resolution (14 bits or higher), is inexpensive and low power. The biggest disadvantage is the fact that the result of conversion depends on the resistor R1 and capacitor C1 used. In order to be independent of these values dual-slope architecture should be used.


  1. Baker R. Jacob, CMOS Circuit Design, Layout, and Simulation, 3rd Edition, 2010, John Wiley & Sons

  2. Camenzind H., Designing Analog Chips, February 2005

  3. Maloberti Franco, Data Converters, 2007, Springer

  4. Norsworthy S.R., Schreier R., Temes G.C., Delta-sigma Data Converters Theory, Design, and Simulation, 1997

  5. http://en.wikipedia.org/wiki/Delta-sigma_modulation

    Delta-sigma modulation (link available 2015.06)

  6. http://pdfserv.maximintegrated.com/en/an/AN634.pdf

    Maxim Integrated Products, Inc., TUTORIAL 634: Pipeline ADCs Come of Age, Nov 20, 2001 (link available 2015.06)

  7. http://pdfserv.maximintegrated.com/en/an/TUT810.pdf

    Maxim Integrated Products, Inc., TUTORIAL 810: UNDERSTANDING FLASH ADCS, (link available 2015.05)

  8. http://www.asdlib.org/onlineArticles/elabware/Scheeline_ADC/ADC_ADC.html#ADCMain

    Scheeline Alexander, Analog to Digital Conversion, (link available 2015.05)

  9. http://www.cypress.com/?id=4&rID=32117

    Document titled “Definitions of INL and DNL in an ADC” (link available 2015.05)

    Direct link to document: http://www.cypress.com/?docID=32695 (link available 2015.05)

  10. http://www.maximintegrated.com/en/app-notes/index.mvp/id/283

    Maxim Integrated Products, Inc., TUTORIAL 283: INL/DNL Measurements for High-Speed Analog-to-Digital Converters (ADCs) (link available 2015.05)

  11. http://www.maximintegrated.com/en/app-notes/index.mvp/id/1023

    Maxim Integrated Products, Inc., TUTORIAL 1023: Understanding Pipelined ADCs (link available 2015.05)

  12. http://www.maximintegrated.com/en/app-notes/index.mvp/id/1870

    Maxim Integrated Products, Inc., TUTORIAL 1870: Demystifying Delta-Sigma ADCs (link available 2015.06)