Tags: ADC, analogtodigital converter, cmos, education, integrating, singleslope, theory
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Abstract:
“The Summary” section presents the architecture of the singleslope integrating ADC with its advantages and disadvantages listed. “The Story” section explains the singleslope integrating architecture. The architecture is thoroughly analyzed. The advantages and disadvantages of the architecture are discussed.
THE SUMMARY
Figure 24: The singleslope integrating ADC.
Advantages:

resolution:

able to achieve 14 bits or higher [3, 7]


applications:

used in highresolution applications [1, 3]

commonly found in slowspeed, low cost applications [1]

digital multimeters

panel meters

voltage or current meters

monitoring DC signals in the instrumentation and industrial markets [7]



very inexpensive to produce [1]

low power consumption [3, 7]

very low offset and gain errors

highly linear

good noise performance [3]
Remarks:

the increase in number of bits doubles the conversion time [7]

the input signal value is converted into a number of clock pulses

competes with sigmadelta converters [7]

architecture:

sampleandhold circuit

integrator

comparator

control logic block

counter

latches


sources of accuracy errors:

sampleandhold circuit

negative reference voltage V_{REF}

resistor R1

capacitor C1

f_{clk_2}

opamp:

offset voltage

bandwidth

finite gain


comparator:

offset voltage

latency


Disadvantages:

slow conversion [1, 3, 7]

typically less than a few hundred samples per second


sensitive (direct dependence of the digital output) to the values of:

resistor R_{1}

capacitor C_{1}

negative reference voltage V_{REF}

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THE STORY
The schematic of the singleslope integrating ADC, is presented in Fig. 25. The singleslope integrating ADC consists of a sampleandhold circuit, an integrator, a comparator, a control logic, a counter and latches.
Figure 25: The singleslope integrating ADC.
Notice, that V_{IN} is positive and V_{REF} is negative. To convert positive voltages, a negative reference is needed. For negative input voltages, a positive referenced is needed.
During the sample phase, the input signal V_{IN} is sampled by the sampleandhold circuit. “Reset” signal is high, thus the counter block is set to 0 and the switch S_{1} is closed, hence the voltage across the capacitor C_{1} is equal to 0 V. The comparator output voltage V_{comparator} is high.
When the hold phase begins, “reset” signal is set low. As a result, the counter starts counting clk_2 clock pulses, switch S_{1} is opened and the integrator begins to work. I_{1} current, that charges capacitor C_{1}, is equal to:
The integrator output voltage V_{1} rises linearly and follows the equation:
The integrator output voltage V_{1} rises until it reaches V_{sampled} value. Hence the conversion time t_{c} is equal to:
It is worth to notice, that the conversion time t_{c} depends on the sampled input signal value V_{sampled}. The higher the sampled voltage V_{sampled}, the longer the conversion time. See Fig. 26.
Figure 26: Plot of V_{1} voltage in the singleslope integrating ADC – example of conversions.
When the integrator output voltage V_{1} reaches V_{sampled} value, the comparator output voltage V_{comparator} goes low. This is the signal for the control logic block to latch outputs of the counter and then set the “reset” signal high. Again, the counter is set to zero and the voltage across capacitor C_{1} is equal to 0 V. The sampleandhold circuit is able to sample the next input voltage value and the ADC is ready to process the sampled value. The result of the conversion, Nbit output digital word b_{N1}b_{N2}…b_{1}b_{0} can be read from the outputs of latches.
During the conversion time t_{c}, the counter counts clk_2 clock pulses. The number of clk_2 clock pulses is directly proportional to the V_{sampled} value. The number of clk_2 clock pulses is the final result of the conversion. For that reason, the clk_2 clock frequency must be many times faster than the bandwidth of the input signal.
The maximum value of Nbit counter is the Nbit chain of ones, that is, 11…11. Its corresponding value in the decimal system is equal to 2^{N} – 1. The counter can count 2^{N} – 1 clk_2 clock pulses maximally. As a result, the maximum conversion time is equal to:
Consequently, the minimum conversion frequency is equal to:
The minimum conversion frequency f_{c_min} should be at least two times greater than the frequency of the input signal (Nyquist’s sampling theorem). For example, when the input signal frequency is equal to 10 kHz, f_{c_min} should be equal to 20 kHz. That means that t_{c_max} should be equal to:
If 10bit singleslope integrating ADC is going to be constructed, that means that clk_2 clock period should be equal to:
Thus, the clk_2 clock frequency in 10bit singleslope integrating ADC for 10 kHz input signal should be equal to:
If we exchange V_{IN} and V_{REF} connections, we can use the biggest advantage of the integrating converter – its ability to average the input signal due to the fact that the input voltage is applied to the integrator. This attribute is used in applications where the input signal is distorted by a noise. The noise averages and the voltage level of an input signal can be measured.
Figure 27: Plot of V_{1} voltage in the singleslope integrating ADC – example of conversions.
The biggest disadvantage of the singleslope architecture is the fact that the conversion time depends on values of capacitor C_{1}, resistor R_{1} and the value of negative voltage reference V_{REF} – see Eq. 1 . In integrated circuits, the values of the designed capacitor or resistor can change typically as +/ 20%. But there is a solution to this problem. The enhanced architecture is called the dualslope integrating ADC.
Conclusion:
The singleslope ADC architecture has the advantage to average noise of the input signal. Moreover, it achieves high resolution (14 bits or higher), is inexpensive and low power. The biggest disadvantage is the fact that the result of conversion depends on the resistor R_{1} and capacitor C_{1} used. In order to be independent of these values dualslope architecture should be used.
References:

Baker R. Jacob, CMOS Circuit Design, Layout, and Simulation, 3^{rd} Edition, 2010, John Wiley & Sons

Norsworthy S.R., Schreier R., Temes G.C., Deltasigma Data Converters Theory, Design, and Simulation, 1997

http://en.wikipedia.org/wiki/Deltasigma_modulation
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http://pdfserv.maximintegrated.com/en/an/AN634.pdf
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http://pdfserv.maximintegrated.com/en/an/TUT810.pdf
Maxim Integrated Products, Inc., TUTORIAL 810: UNDERSTANDING FLASH ADCS, (link available 2015.05)

http://www.asdlib.org/onlineArticles/elabware/Scheeline_ADC/ADC_ADC.html#ADCMain
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http://www.cypress.com/?id=4&rID=32117
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http://www.maximintegrated.com/en/appnotes/index.mvp/id/283
Maxim Integrated Products, Inc., TUTORIAL 283: INL/DNL Measurements for HighSpeed AnalogtoDigital Converters (ADCs) (link available 2015.05)

http://www.maximintegrated.com/en/appnotes/index.mvp/id/1023
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http://www.maximintegrated.com/en/appnotes/index.mvp/id/1870
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