Tags: CMOS, silicon, technology

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Silicon

intrinsic carriers nithe number of electrons in the conduction band (and as a result the number of holes in the valence band) at a given time. At room temperature :

ni ~= 14.5 x 109 carriers/cm3

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For intrinsic silicon:

n =p = ni ~= 14.5 x 109 carriers/cm3

where:

  • n – the number of electrons in the conduction band of silicon

  • p – the number of holes in the valence band of silicon

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Compare this number to the number of silicon atoms, NSi, in a given volume of crystalline silicon:

NSi = 50 x 1021 atoms/cm3

That means, that there is only one excited electron/hole pair for every 1012 silicon atoms.

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Technologies / processes

  • n-well process: p-type substrate for NMOS transistors and n-well for PMOS transistors

  • p-well process: n-type substrate for PMOS transistors and p-well for NMOS transistors

  • twin tube process: uses both n-well and p-well

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twin-tub (twin-well) vs triple-tub (triple-well) process:

http://wiki.usgroup.eu/wiki/_media/public/tutorials/cduarte/cmos-fabrication-process-types-02.png

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[Baker] “The thickness of a wafer is typically 500 um, while the thickness of a grown oxide or a deposited resist may be only a um (10-6 m) or even less.”

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Resist processes:

  • a positive resist process – the area that was illuminated was removed

  • a negative resist process – removes the areas of resist that were not exposed to the light.

[Baker] ”Using both types of resist allows the process designer to cut down on the number of masks needed to define a CMOS process. Because creating the masks is expensive, lowering the number of masks is equated with lowering the cost of a process. This is also important in large manufacturing plants where fewer steps equal lower cost.”

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Resources:

  • Baker R. Jacob, CMOS Circuit Design, Layout, and Simulation, 3rd Edition, 2010, John Wiley & Sons