Tags: ADC, analog-to-digital converter, cmos, education, pipeline, SAR, successive approximation register, theory

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Abstract:

          “The Summary” section presents the architecture of the successive approximation (SAR) ADC with its advantages and disadvantages listed. “The Story” section explains the SAR architecture. The SAR architecture is compared with flash, two-step flash and pipeline architectures. Advantages and disadvantages of the SAR architectures are analyzed.

 

THE SUMMARY

 

successive approximation SAR adc

Figure 21: The successive approximation (SAR) ADC.

 

Advantages:

  • one of the most popular approaches for ADC implementation

  • reasonably quick conversion time

  • relatively high accuracy

    • available in resolutions up to 16 bits [7]

  • low power

  • small area, low cost

  • modest circuit complexity

 

Remarks:

  • the increase in number of bits results in:

    • approximately linear increase of the conversion time [7]

    • linear increase of the die size [7]

  • architecture:

    • a sample-and-hold circuit

    • a comparator

    • a control logic block

    • N-bit DAC

  • sources of accuracy errors:

    • offset voltage of a comparator

    • accuracy of DAC circuit

 

Disadvantages:

  • medium speed:

    • operates iteratively

    • each single N-bit conversion requires N clock cycles

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THE STORY

 

The schematic of the successive approximation ADC, called SAR ADC, is presented in Fig. 22. The successive approximation ADC consists of a sample-and-hold circuit, a comparator, a control logic block and a DAC circuit. Yes, a DAC circuit is implemented in the ADC architecture!

The input signal VIN is sampled by a sample-and-hold circuit. During the hold phase of the sample-and-hold circuit (clk_1 low), the sampled signal V1 is converted into N-bit digital output code.

 

The conversion algorithm is as follows:

  1. MSB (most significant) bit of the output digital code is set to “1”, thus DAC output voltage V2 is set to half of the power supply VDD, that is, VDD/2.

  2. The sampled input signal V1 is compared by a comparator with DAC output voltage V2.

  3. The result of comparison, that is V3 voltage, is processed by the Control Logic block. If the comparator output V3 voltage is equal to “1”, 2nd bit of the N-bit digital output code is set to “1” and DAC output is moved up to ¾ VDD. If the comparator output V3 is equal to “0”, 2nd bit of the N-bit digital output code is set to “0” and DAC output is moved down to ¼ VDD.

  4. The sampled input signal V1 is compared again by a comparator with new DAC output voltage V2. The new result of comparison is analyzed by the Control Logic block and N-bit digital output code and DAC output are set accordingly.

  5. The conversion process lasts N clk_2 clock cycles and results in N-bit digital output code.

 

An example of the conversion process for 3-bit SAR ADC is illustrated in Fig. 23. Power supply VDD is equal to 4 V, input signal VIN is equal to 2.2 V. Thus the final digital output code is equal to 100.

 

successive approximation SAR adc

Figure 22: The successive approximation (SAR) ADC.

 

          The successive approximation ADC is slow comparing to the flash ADC, the two-step flash ADC and the pipeline ADC. In SAR ADC architecture, every single conversion of an analog signal into its digital representation takes N clk_2 clock cycles, whereas in the pipeline ADC, the first digital code is available after N clock cycles, but every next digital code is available every clock cycle. On the other hand, the SAR ADC consumes lower power and takes up a smaller area, due to its simplicity.

 

successive approximation SAR adc - conversion

Figure 23: The conversion of 3-bit successive approximation ADC. Power supply VDD and input signal VIN are equal to 4 V and 2.2 V, respectively.

 

Conclusion:

          The SAR is one of the most popular architecture of ADCs due to its simplicity and small area. However, the SAR architecture operates iteratively, thus the result of each conversion appears after N-clock cycles. On the other hand, the SAR ADC still offers medium to high speed with medium to high resolutions (up to 16 bits).

 

References:

  1. Baker R. Jacob, CMOS Circuit Design, Layout, and Simulation, 3rd Edition, 2010, John Wiley & Sons

  2. Camenzind H., Designing Analog Chips, February 2005

  3. Maloberti Franco, Data Converters, 2007, Springer

  4. Norsworthy S.R., Schreier R., Temes G.C., Delta-sigma Data Converters Theory, Design, and Simulation, 1997

  5. http://en.wikipedia.org/wiki/Delta-sigma_modulation

    Delta-sigma modulation (link available 2015.06)

  6. http://pdfserv.maximintegrated.com/en/an/AN634.pdf

    Maxim Integrated Products, Inc., TUTORIAL 634: Pipeline ADCs Come of Age, Nov 20, 2001 (link available 2015.06)

  7. http://pdfserv.maximintegrated.com/en/an/TUT810.pdf

    Maxim Integrated Products, Inc., TUTORIAL 810: UNDERSTANDING FLASH ADCS, (link available 2015.05)

  8. http://www.asdlib.org/onlineArticles/elabware/Scheeline_ADC/ADC_ADC.html#ADCMain

    Scheeline Alexander, Analog to Digital Conversion, (link available 2015.05)

  9. http://www.cypress.com/?id=4&rID=32117

    Document titled “Definitions of INL and DNL in an ADC” (link available 2015.05)

    Direct link to document: http://www.cypress.com/?docID=32695 (link available 2015.05)

  10. http://www.maximintegrated.com/en/app-notes/index.mvp/id/283

    Maxim Integrated Products, Inc., TUTORIAL 283: INL/DNL Measurements for High-Speed Analog-to-Digital Converters (ADCs) (link available 2015.05)

  11. http://www.maximintegrated.com/en/app-notes/index.mvp/id/1023

    Maxim Integrated Products, Inc., TUTORIAL 1023: Understanding Pipelined ADCs (link available 2015.05)

  12. http://www.maximintegrated.com/en/app-notes/index.mvp/id/1870

    Maxim Integrated Products, Inc., TUTORIAL 1870: Demystifying Delta-Sigma ADCs (link available 2015.06)