Tags: ADC, analog-to-digital converter, cmos, education, pipeline, theory

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Abstract:         

          “The Summary” section presents the architecture of the pipeline ADC with its advantages and disadvantages listed. “The Story” section explains the pipeline architecture. The pipeline architecture is referenced to the flash and two-step flash architectures. Advantages and disadvantages of the pipeline architectures are analyzed. Possibilities to construct N-stage 1 bit architecture or N-stage M-bit architectures are presented.

 

THE SUMMARY

 

pipeline adc - additional sample-and-hold

Figure 17: The pipeline ADC.

 

Advantages:

  • high resolution (8-14 bits) at relatively fast speeds (100 MSPS) [1, 7]

    • the first code is available after the latency equal to N clock cycles. Then every next code is available every clock cycle.

 

Remarks:

  • the increase in number of bits results in:

    • approximately linear increase of the conversion time [7]

    • linear increase of the die size [7]

  • architecture:

    • M stages of N-bit flash ADCs:

      • M x 2N/2 resistors

      • M x (2N/2 – 1) comparators

    • DAC circuit

    • subtractor

    • two non-overlapping clocks

    • buffers can be desired

  • sources of accuracy errors:

    • the same as in the two-step flash ADC:

      • the same as in the flash ADC:

        • matching of resistors

        • offset voltage of comparators

      • subtractor and buffers – problems of an opamp like:

        • offset voltage

        • finite gain

        • bandwidth

        • stability

 

Disadvantages:

  • the first code is available after the latency equal to N clock cycles (see “Advantages” section above)

  • the error from any stage propagates through the succeeding stages

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THE STORY

 

Traditionally, the pipeline ADC consists of N 1-bit stages. Pipeline ADCs achieve high resolution (10-13 bits) at relatively fast speeds. The disadvantage of this architecture is the fact that the first code is available after N clock cycles. However, then every next code is available every clock cycle, due to the fact that when the output voltage of the first stage is passed to the second stage, the first stage can process the new voltage value while the second stage works on the voltage passed by the first stage. Each stage operates on the voltage passed by by the previous stage.

          Whether the initial delay equal to N clock cycles is a problem, depends on the application.

 

pipeline adc

Figure 18: The pipeline ADC.

 

          As it is seen in Fig. 19, every stage of the pipeline ADC consists of a sample-and-hold circuit, 1-bit flash ADC, 1-bit DAC, a subtractor and an amplifier by 2.

 

pipeline adc - comments

Figure 19: The pipeline ADC architecture with marked 1-bit flash ADC and 1-bit DAC. A single pipeline stage is also marked.

 

          One stage of the pipeline ADC architecture in Fig. 19 is almost exactly the same as the two-step flash ADC architecture in Fig. 12. Thus, the problem regarding the two-step flash ADC architecture in Fig. 12, relates to the pipeline ADC architecture in Fig. 19 (see the discussion for the two-step flash ADC architecture). The solution with additional sample-and-hold circuits and the additional clk_2 clock applies to the pipeline architecture as well – see Fig. 20.

 

pipeline adc - additional sample-and-hold

Figure 20: The pipeline ADC architecture from Fig. 18 with additional sample-and-hold circuits.

 

The pipeline ADC stages can have more bits than only one. Every stage can have any number of bits, that is, they can consist of any M-bit flash ADC. Every stage can even have different number of bits than the rest stages. However, it is good to choose the same number of bits for each stage. One stage may be designed and copied to achieve required resolution. It is less time consuming.

Two-step flash may be called a pipeline ADC. Two-step flash consists of two stages of M-bit flash ADCs.

The accuracy of the pipeline ADC depends the most on the first stages. The error from the first stages propagates through all the succeeding stages as it was seen in the two-step ADC (see the discussion regarding Fig. 16). The error from any stage propagates through the succeeding stages.

The advantage of the pipeline architecture is, as in the case of two-step flash architecture, reduced power consumption and die area comparing to the flash ADC. The cost of this improvement is the reduced speed of the conversion. However, the pipeline architecture propose interesting combination of speed, resolution, power consumption and die area.

 

 

Conclusion:

          The pipeline ADC is, as in the case of the two-step flash ADC, the natural improvement of the flash ADC architecture. It is an answer to improve resolution and decrease power consumption and occupied area. The cost of these improvements is reduced speed of conversion. The conversion takes more steps instead of one as in the case of the flash architecture. The pipeline architecture offers a lot of flexibility to choose number of stages and the resolution of each stage. This architecture offers interesting combination of speed, resolution, power consumption and die area.

 

References:

  1. Baker R. Jacob, CMOS Circuit Design, Layout, and Simulation, 3rd Edition, 2010, John Wiley & Sons

  2. Camenzind H., Designing Analog Chips, February 2005

  3. Maloberti Franco, Data Converters, 2007, Springer

  4. Norsworthy S.R., Schreier R., Temes G.C., Delta-sigma Data Converters Theory, Design, and Simulation, 1997

  5. http://en.wikipedia.org/wiki/Delta-sigma_modulation

    Delta-sigma modulation (link available 2015.06)

  6. http://pdfserv.maximintegrated.com/en/an/AN634.pdf

    Maxim Integrated Products, Inc., TUTORIAL 634: Pipeline ADCs Come of Age, Nov 20, 2001 (link available 2015.06)

  7. http://pdfserv.maximintegrated.com/en/an/TUT810.pdf

    Maxim Integrated Products, Inc., TUTORIAL 810: UNDERSTANDING FLASH ADCS, (link available 2015.05)

  8. http://www.asdlib.org/onlineArticles/elabware/Scheeline_ADC/ADC_ADC.html#ADCMain

    Scheeline Alexander, Analog to Digital Conversion, (link available 2015.05)

  9. http://www.cypress.com/?id=4&rID=32117

    Document titled “Definitions of INL and DNL in an ADC” (link available 2015.05)

    Direct link to document: http://www.cypress.com/?docID=32695 (link available 2015.05)

  10. http://www.maximintegrated.com/en/app-notes/index.mvp/id/283

    Maxim Integrated Products, Inc., TUTORIAL 283: INL/DNL Measurements for High-Speed Analog-to-Digital Converters (ADCs) (link available 2015.05)

  11. http://www.maximintegrated.com/en/app-notes/index.mvp/id/1023

    Maxim Integrated Products, Inc., TUTORIAL 1023: Understanding Pipelined ADCs (link available 2015.05)

  12. http://www.maximintegrated.com/en/app-notes/index.mvp/id/1870

    Maxim Integrated Products, Inc., TUTORIAL 1870: Demystifying Delta-Sigma ADCs (link available 2015.06)