Tags: cleanroom, design, Electron Beam Lithography (EBL), HSQ, nanowires, Nanowire Junctionless Transistor (NJT), operational amplifier, poly-silicon on insulator (POI), process control structures, SPICE, silicon, silicon on insulator (SOI), split-cross bridge resistor, Vertical-Slit Field-Effect Transistor (VeSFET)
As consecutive technology nodes are reached by the traditional silicon CMOS (complementary metal–oxide–semiconductor) technology, microelectronic industry’s interest in junctionless transistors grows. Shrinking the channel of the traditional junction-based transistor leads to snew challenges and increasing manufacturing costs. Nanometer junctionless field effect transistor can be the answer to growing problems with the traditional MOS transistors.
In this work a simple SPICE level 2 model for VeSFET junctionless transistor (Vertical Slit Field-Effect Transistor ) is proposed. This model serves to assess parameters of an operational amplifier built using VeSFET transistors. The circuit exhibits good results, thus an attempt to manufacture a junctionless transistor is made. Process flow, architecture and measurements of proposed junctionless transistor are presented. In the chosen architecture of junctionless transistor the length of the nanowire does not depend on the gate width. All process steps are commonly used in present CMOS technologies. Wide range of dimensions is investigated. Widths equal to 10 – 60 nm and lengths equal to 20 nm – 10 μm are covered. Both poly-silicon on insulator (POI) and silicon on insulator (SOI) wafers are used.
Nanowire junctionless transistors manufactured on POI wafers exhibit Ion / Ioff ratio of about 5 decades, leakage current is in order of tens of pA and the best subthreshold slope is equal to 140 mV/dec. The value of subthreshold slope is improved on SOI wafers and is lower than 100 mV/dec.