Tags: ADC, cmos, education, flash, sparkle codes, sparkles, theory, thermometer bubbles, thermometer code



          “The Summary” section provides the architecture of the flash ADC with its advantages and disadvantages listed. “The Story” section explains the flash architecture. Example of 3-bit converter and its transfer curve are presented. Concepts of “thermometer code”, “thermometer bubbles” and “sparkle codes” are discussed. Advantages and disadvantages of the flash architecture are presented. The way to manage big input capacitance of the flash converter is also included.




flash adc - architecture

Figure 2: Flash ADC.


  • the fastest ADC

    • speed depends on the speed of comparators (after what time a comparator gives a result of comparison)

    • sampling rates more than 1 GSPS are possible [7]

    • the conversion time does not change considerably when the number of bits is increased

  • ideal for applications requiring very large bandwidth:

    • data-acquisition [7]

    • satellite communication [7]

    • radar processing [7]

    • sampling oscilloscopes [7]

    • high-density disk drivers [7]



  • usually limited to high-speed applications that cannot be addressed in any other way

  • architecture:

    • 2N resistors

    • 2N – 1 comparators

  • sources of accuracy errors:

    • matching of resistors

    • offset voltage of comparators



  • low resolution

    • traditionally limited to 8-bit resolution [1, 7]

  • every bit doubles the area and power requirements

    • the biggest area

    • the highest power consumption

  • every bit doubles the input capacitance

  • thermometer-code bubbles / sparkle codes





          Fig. 3 presents the flash ADC architecture called also a parallel converter. It consists of a resistor ladder and comparators. The resistor ladder provides voltage references to comparators. The input signal is compared by comparators and the outputs of comparators are coded into N-bit code.


flash adc - architecture

Figure 3: Flash ADC.


          Fig. 4 reveals more details. The resistor ladder is connected to the power supply VDD from the top and to the ground VGND from the bottom. It is worth to mention that the resistor ladder can be connected to any other values, both form the top and the bottom. Here, it is assumed that the input signal VIN is rail-to-rail signal (from VDD to VGND).

          The N-bit flash ADC consists of 2N resistors and 2N – 1 comparators. There is one comparator less than the total number of resistors.

          It is worth to notice that the source of VIN is loaded by the input capacitance of comparators. The more comparators are used, that is the more bits are implemented in the ADC, the bigger the input capacitance is.


flash adc - notes

Figure 4: N-bit flash ADC – notes added.


          Let’s consider 3-bit flash ADC. Its schematic is presented in Fig. 5. The ADC consists of 8 resistors and 7 comparators. When the input signal VIN is equal to 2.75 V and the power supply VDD is equal to 4 V, outputs of first five comparators are equal to 4 V (power supply VDD) and the outputs of the last two comparators are equal to 0 V (ground). This situation is presented in Fig. 6.


flash adc - 3 bits adc

Figure 5: 3-bit flash ADC.


flash adc - 3 bits adc - example

Figure 6: 3-bit flash ADC – example where VDD is equal 4 V and the input signal VIN is equal 2.75 V.


          From the digital point of view, if the value of an analog signal is equal to the power supply VDD, its value is equal to “1”. Similarly, when the value of an analog signal is equal to the ground VGND, in the digital world its value is equal to “0”. In order to present outputs of comparators from Fig. 6 in a more convenient way, “4 V” can be changed to “1” and “0 V” can be changed to “0”. Table 1 shows all possible combinations of the input signal VIN, their corresponding outputs of comparators and output digital codes.

          The transfer curve of the 3-bit flash ADC from Fig. 6 is presented in Fig. 7.


Table 1: All possible input signal VIN values, their corresponding outputs of comparators and output digital codes.

1.1.table - flash adc - 3 bits adc - example


flash adc - 3 bits adc - conversion curve

Figure 7: Transfer curve for 3-bit flash ADC from Fig. 6


       The outputs of the comparators in the flash ADC architecture create so called a thermometer code. The name is from the mercury thermometer, where the mercury is present to the point of the measured temperature, and above this level there is no mercury. Similarly, in the flash ADC, there is a chain of ones “1”, above which is a chain of zeros “0” as seen in Table 1. The thermometer code is then coded into a desired digital output code.

          The biggest advantage of the flash ADC architecture is the speed of comparison. The value of the input signal must be “decoded” only by comparators. The outputs of comparators are then processed by digital part of the block.

       Flash ADCs have the highest speed of any type of ADCs. However every bit doubles the area (number of resistors and comparators) and power. As it was seen above, 3-bit flash ADC needs 7 comparators. 4-bit flash ADC needs 15 comparators, 5-bit – 31, 6-bit – 63, 7-bit – 127, 8-bit – 255 and so on. According to [1], “flash converters have traditionally been limited to 8-bit resolution with conversion speeds of 10-40 Ms/s using CMOS technology”.

       Another problem is the fact that every bit doubles the input capacitance – number of comparators doubles. Sometimes the high input capacitance can be problematic. Instead of making the source of the input signal more current efficient, buffers can be used to transfer the input signal to comparators. However, the speed of the ADC decreases (now the input signal path is a buffer and a comparator) and the area and the power consumption increase. The idea is shown in Fig. 8. Of course the buffers can drive any number of comparators not just two as seen in Fig. 8.


flash adc - buffers

Figure 8: Usage of buffers to transfer the input signal VIN to comparators in a situation when the input capacitance of the flash ADC is too big for the source of VIN.


          The offset of the comparators should be smaller than an LSB of the ADC. Typically, the comapartors are low-offset comparators.

          Typically, a thermometer code is present at the outputs of comparators. However, due to a latency mismatch of comparators for high sampling frequencies or due to the nature of the input signal, a false zero can appear anywhere in the thermometer code. For example, instead of 000 1111 at the outputs of the comparators for 3-bit ADC, 000 1011 may be present and latched as a result of comparison. The out-of-sequence 0 or 1 is called a sparkle or a thermometer bubble. Sparkle codes can be eliminated by using track-and-hold circuit at the input of an ADC combined with a proper encoding technique [7].

          Another issue in flash ADCs is the problem of metastability. The digital output is defined as metastable when its value is unclear, that is, when its value is neither “1” nor “0”. The outputs of comparators should be designed carefully to not exhibit the problem of metastability. The problem of metastability is greater when a metastable output drives two circuits. It is possible that Circuit A sees “0” on its input, while Circuit B sees “1”. To eliminate this problem a potentially metastable output should drive only one circuit.



          Flash ADCs are the fastest ADCs. They support sampling rates more than 1 GSPS. The conversion time does not change considerably when the number of bits increases. However, flash ADCs are traditionally limited to 8-bit resolution, due to the fact that they occupy the biggest area, exhibit the highest power consumption and have the biggest input capacitance. They are usually used in the high-speed applications that cannot be addressed in any other way. Thermometer bubbles may be present when using this architecture. Sample-and-hold or track-and-hold circuits at the input of the ADC may be helpful.



  1. Baker R. Jacob, CMOS Circuit Design, Layout, and Simulation, 3rd Edition, 2010, John Wiley & Sons

  2. Camenzind H., Designing Analog Chips, February 2005

  3. Maloberti Franco, Data Converters, 2007, Springer

  4. Norsworthy S.R., Schreier R., Temes G.C., Delta-sigma Data Converters Theory, Design, and Simulation, 1997

  5. http://en.wikipedia.org/wiki/Delta-sigma_modulation

    Delta-sigma modulation (link available 2015.06)

  6. http://pdfserv.maximintegrated.com/en/an/AN634.pdf

    Maxim Integrated Products, Inc., TUTORIAL 634: Pipeline ADCs Come of Age, Nov 20, 2001 (link available 2015.06)

  7. http://pdfserv.maximintegrated.com/en/an/TUT810.pdf

    Maxim Integrated Products, Inc., TUTORIAL 810: UNDERSTANDING FLASH ADCS, (link available 2015.05)

  8. http://www.asdlib.org/onlineArticles/elabware/Scheeline_ADC/ADC_ADC.html#ADCMain

    Scheeline Alexander, Analog to Digital Conversion, (link available 2015.05)

  9. http://www.cypress.com/?id=4&rID=32117

    Document titled “Definitions of INL and DNL in an ADC” (link available 2015.05)

    Direct link to document: http://www.cypress.com/?docID=32695 (link available 2015.05)

  10. http://www.maximintegrated.com/en/app-notes/index.mvp/id/283

    Maxim Integrated Products, Inc., TUTORIAL 283: INL/DNL Measurements for High-Speed Analog-to-Digital Converters (ADCs) (link available 2015.05)

  11. http://www.maximintegrated.com/en/app-notes/index.mvp/id/1023

    Maxim Integrated Products, Inc., TUTORIAL 1023: Understanding Pipelined ADCs (link available 2015.05)

  12. http://www.maximintegrated.com/en/app-notes/index.mvp/id/1870

    Maxim Integrated Products, Inc., TUTORIAL 1870: Demystifying Delta-Sigma ADCs (link available 2015.06)