Tags: ADC, analogtodigital converter, cmos, dualslope, education, integrating, theory
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Abstract:
“The Summary” section presents the architecture of the dualslope integrating ADC with its advantages and disadvantages listed. “The Story” section explains the dualslope integrating architecture. The architecture is thoroughly analyzed. The advantages and disadvantages of the architecture are discussed.
THE SUMMARY
Figure 28: The dualslope integrating ADC.
Advantages:

used in highresolution applications [1, 3]

able to achieve 14 bits or higher [3, 7]


very inexpensive to produce [1]

commonly found in slowspeed, low cost applications [1]

digital multimeters

panel meters

voltage or current meters

monitoring DC signals in the instrumentation and industrial markets [7]



very low offset and gain errors

highly linear

low power consumption [3]

good noise performance [3]

independent of capacitor C_{1} and resistor R_{1} values

the increase in number of bits does not change die size considerably [7]
Remarks:

the increase in number of bits doubles the conversion time [7]

the input signal value is converted into a number of clock pulses

competes with sigmadelta converters [7]

architecture:

sampleandhold circuit

integrator

comparator

control logic block

counter

latches


sources of accuracy errors:

sampleandhold circuit

reference voltage V_{REF}

f_{clk_2}

opamp:

offset voltage

bandwidth

finite gain


comparator:

offset voltage

latency


Disadvantages:

slow conversion [1, 3, 7]

typically less than a few hundred samples per second


total conversion time longer than in singleslope architecture, but now the conversion time is independent of capacitor C_{1} and resistor R_{1} values

sensitive to the values of:

reference voltage V_{REF}

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THE STORY
The schematic of the dualslope integrating ADC is presented in Fig. 29. The architecture is almost identical to the singleslope version, except the fact that the positive input of comparator is now grounded and the sampled value V_{sampled} is connected to the input of the integrator through a switch. The control logic block chooses whether the reference voltage V_{REF} or the sampled voltage V_{sampled} is connected to the input of the integrator. Remember, for positive input signal values V_{IN} a negative reference voltage V_{REF} is needed. For negative input signal values V_{IN} a positive reference voltage V_{REF} is needed.
Figure 29: The dualslope integrating ADC.
The biggest improvement in the dualslope architecture comparing to the singleslope architecture is the fact that the conversion time is independent of the values of capacitor C_{1} and resistor R_{1}. Let’s see how it is done.
Similarly to the singleslope architecture, during the sample phase the input voltage V_{IN} is sampled and the “reset” signal is high. The counter is set to 0 and the switch S_{1} is closed. The voltage across the capacitor C_{1} is equal to 0 V, thus V_{1} is also equal to 0 V.
When the hold phase starts, the “reset” signal is set low. The switch S_{2} must now connect the V_{sampled} voltage to the input of the integrator. The current through resistor R_{1} is equal to:
The current I_{1} charges the C_{1} capacitor, hence V_{1} voltage rises linearly as:
∆t is a constant known chosen value, controlled by the control logic block, and is equal to T_{1}, thus:
V_{1} voltage rises linearly for T_{1} time and after this time a known positive voltage value is applied to the input of the integrator by switching the switch S_{2} to V_{REF} voltage. Now, I_{1} voltage is equal to:
and the voltage V_{1} drops linearly as:
until it achieves 0 V. When V_{1} drops to 0 V, the comparator output voltage V_{comparator} goes low, and this is the signal for the control logic block to latch the outputs of latches and then to set signal “reset” high. Again, the counter is set to 0 V and switch S_{1} is closed, thus V_{1} voltage is kept on the level of 0V.
∆V_{1} in Eq. 3 is a know value. It is equal to the voltage value that C_{1} was charged during T_{1} – see Eq. 2. Thus ∆t, that is the conversion time, can be calculated as:
Now, the conversion time t_{c} is independent of resistor R_{1} and capacitor C_{1}. The conversion time is proportional to the input voltage V_{IN} as it should be (see Fig. 30 and 31) and to the T_{1} time that is know and fixed. The conversion time depends also on V_{REF} voltage as in the singleslope architecture.
As in the singleslope architecture, the input voltage value after the conversion is represented by Nbit digital word b_{N1}b_{N2}…b_{1}b_{0} that is equal to number of clk_2 clock pulses counted during the conversion time t_{c}.
Again as in the case of singleslope architecture, the dualslope integrating ADC has an ability to average noise present on the input signal. This can be useful in noisy industrial environments in applications where high update rates are not required.
Figure 30: Plot of V_{1} voltage in the dualslope integrating ADC – example of conversions.
Figure 31: Plot of V_{1} voltage in the dualslope integrating ADC – example of conversions with notes.
Conclusion:
The dualslope ADC architecture has the advantage to average noise of the input signal. Moreover, it achieves high resolution (14 bits or higher), is inexpensive and low power. The dualslope architecture is slower than the singleslope architecture due to the fact that the conversion is done into two steps and not in one as in the case of singleslope architecture, but now the result of conversion is independent of the resistor R_{1} and capacitor C_{1}.
References:

Baker R. Jacob, CMOS Circuit Design, Layout, and Simulation, 3^{rd} Edition, 2010, John Wiley & Sons

Norsworthy S.R., Schreier R., Temes G.C., Deltasigma Data Converters Theory, Design, and Simulation, 1997

http://en.wikipedia.org/wiki/Deltasigma_modulation
Deltasigma modulation (link available 2015.06)

http://pdfserv.maximintegrated.com/en/an/AN634.pdf
Maxim Integrated Products, Inc., TUTORIAL 634: Pipeline ADCs Come of Age, Nov 20, 2001 (link available 2015.06)

http://pdfserv.maximintegrated.com/en/an/TUT810.pdf
Maxim Integrated Products, Inc., TUTORIAL 810: UNDERSTANDING FLASH ADCS, (link available 2015.05)

http://www.asdlib.org/onlineArticles/elabware/Scheeline_ADC/ADC_ADC.html#ADCMain
Scheeline Alexander, Analog to Digital Conversion, (link available 2015.05)

http://www.cypress.com/?id=4&rID=32117
Document titled “Definitions of INL and DNL in an ADC” (link available 2015.05)
Direct link to document: http://www.cypress.com/?docID=32695 (link available 2015.05)

http://www.maximintegrated.com/en/appnotes/index.mvp/id/283
Maxim Integrated Products, Inc., TUTORIAL 283: INL/DNL Measurements for HighSpeed AnalogtoDigital Converters (ADCs) (link available 2015.05)

http://www.maximintegrated.com/en/appnotes/index.mvp/id/1023
Maxim Integrated Products, Inc., TUTORIAL 1023: Understanding Pipelined ADCs (link available 2015.05)

http://www.maximintegrated.com/en/appnotes/index.mvp/id/1870
Maxim Integrated Products, Inc., TUTORIAL 1870: Demystifying DeltaSigma ADCs (link available 2015.06)