Tags: ADC, analog-to-digital converter, cmos, dual-slope, education, integrating, theory

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Abstract:

“The Summary” section presents the architecture of the dual-slope integrating ADC with its advantages and disadvantages listed. “The Story” section explains the dual-slope integrating architecture. The architecture is thoroughly analyzed. The advantages and disadvantages of the architecture are discussed.

THE SUMMARY

dual-slope integrating ADC - schematic

Figure 28: The dual-slope integrating ADC.

 

Advantages:

  • used in high-resolution applications [1, 3]

    • able to achieve 14 bits or higher [3, 7]

  • very inexpensive to produce [1]

    • commonly found in slow-speed, low cost applications [1]

      • digital multi-meters

      • panel meters

      • voltage or current meters

      • monitoring DC signals in the instrumentation and industrial markets [7]

  • very low offset and gain errors

  • highly linear

  • low power consumption [3]

  • good noise performance [3]

  • independent of capacitor C1 and resistor R1 values

  • the increase in number of bits does not change die size considerably [7]

 

Remarks:

  • the increase in number of bits doubles the conversion time [7]

  • the input signal value is converted into a number of clock pulses

  • competes with sigma-delta converters [7]

  • architecture:

    • sample-and-hold circuit

    • integrator

    • comparator

    • control logic block

    • counter

    • latches

  • sources of accuracy errors:

    • sample-and-hold circuit

    • reference voltage VREF

    • fclk_2

    • opamp:

      • offset voltage

      • bandwidth

      • finite gain

    • comparator:

      • offset voltage

      • latency

 

Disadvantages:

  • slow conversion [1, 3, 7]

    • typically less than a few hundred samples per second

  • total conversion time longer than in single-slope architecture, but now the conversion time is independent of capacitor C1 and resistor R1 values

  • sensitive to the values of:

    • reference voltage VREF

=========================================================================

THE STORY

The schematic of the dual-slope integrating ADC is presented in Fig. 29. The architecture is almost identical to the single-slope version, except the fact that the positive input of comparator is now grounded and the sampled value -Vsampled is connected to the input of the integrator through a switch. The control logic block chooses whether the reference voltage VREF or the sampled voltage -Vsampled is connected to the input of the integrator. Remember, for positive input signal values VIN a negative reference voltage -VREF is needed. For negative input signal values -VIN a positive reference voltage VREF is needed.

 

dual-slope integrating ADC - schematic

Figure 29: The dual-slope integrating ADC.

 

       The biggest improvement in the dual-slope architecture comparing to the single-slope architecture is the fact that the conversion time is independent of the values of capacitor C1 and resistor R1. Let’s see how it is done.

    Similarly to the single-slope architecture, during the sample phase the input voltage -VIN is sampled and the “reset” signal is high. The counter is set to 0 and the switch S1 is closed. The voltage across the capacitor C1 is equal to 0 V, thus V1 is also equal to 0 V.

     When the hold phase starts, the “reset” signal is set low. The switch S2 must now connect the -Vsampled voltage to the input of the integrator. The current through resistor R1 is equal to:

 

6. eq. 1

 

The current I1 charges the C1 capacitor, hence V1 voltage rises linearly as:

6. eq. 2

 

∆t is a constant known chosen value, controlled by the control logic block, and is equal to T1, thus:

 

6. eq. 3 v3

 

 

 

V1 voltage rises linearly for T1 time and after this time a known positive voltage value is applied to the input of the integrator by switching the switch S2 to VREF voltage. Now, I1 voltage is equal to:

 

6. eq. 4

 

and the voltage V1 drops linearly as:

 

6. eq. 5 v2

 

 

until it achieves 0 V. When V1 drops to 0 V, the comparator output voltage Vcomparator goes low, and this is the signal for the control logic block to latch the outputs of latches and then to set signal “reset” high. Again, the counter is set to 0 V and switch S1 is closed, thus V1 voltage is kept on the level of 0V.

∆V1 in Eq. 3 is a know value. It is equal to the voltage value that C1 was charged during T1 – see Eq. 2. Thus ∆t, that is the conversion time, can be calculated as:

 

6. eq. 6

 

Now, the conversion time tc is independent of resistor R1 and capacitor C1. The conversion time is proportional to the input voltage VIN as it should be (see Fig. 30 and 31) and to the T1 time that is know and fixed. The conversion time depends also on VREF voltage as in the single-slope architecture.

As in the single-slope architecture, the input voltage value after the conversion is represented by N-bit digital word bN-1bN-2…b1b0 that is equal to number of clk_2 clock pulses counted during the conversion time tc.

 

Again as in the case of single-slope architecture, the dual-slope integrating ADC has an ability to average noise present on the input signal. This can be useful in noisy industrial environments in applications where high update rates are not required.

dual-slope integrating ADC - conversions

Figure 30: Plot of V1 voltage in the dual-slope integrating ADC – example of conversions.

 

dual-slope integrating ADC - conversions notes

Figure 31: Plot of V1 voltage in the dual-slope integrating ADC – example of conversions with notes.

 

Conclusion:

The dual-slope ADC architecture has the advantage to average noise of the input signal. Moreover, it achieves high resolution (14 bits or higher), is inexpensive and low power. The dual-slope architecture is slower than the single-slope architecture due to the fact that the conversion is done into two steps and not in one as in the case of single-slope architecture, but now the result of conversion is independent of the resistor R1 and capacitor C1.

 

 

References:

  1. Baker R. Jacob, CMOS Circuit Design, Layout, and Simulation, 3rd Edition, 2010, John Wiley & Sons

  2. Camenzind H., Designing Analog Chips, February 2005

  3. Maloberti Franco, Data Converters, 2007, Springer

  4. Norsworthy S.R., Schreier R., Temes G.C., Delta-sigma Data Converters Theory, Design, and Simulation, 1997

  5. http://en.wikipedia.org/wiki/Delta-sigma_modulation

    Delta-sigma modulation (link available 2015.06)

  6. http://pdfserv.maximintegrated.com/en/an/AN634.pdf

    Maxim Integrated Products, Inc., TUTORIAL 634: Pipeline ADCs Come of Age, Nov 20, 2001 (link available 2015.06)

  7. http://pdfserv.maximintegrated.com/en/an/TUT810.pdf

    Maxim Integrated Products, Inc., TUTORIAL 810: UNDERSTANDING FLASH ADCS, (link available 2015.05)

  8. http://www.asdlib.org/onlineArticles/elabware/Scheeline_ADC/ADC_ADC.html#ADCMain

    Scheeline Alexander, Analog to Digital Conversion, (link available 2015.05)

  9. http://www.cypress.com/?id=4&rID=32117

    Document titled “Definitions of INL and DNL in an ADC” (link available 2015.05)

    Direct link to document: http://www.cypress.com/?docID=32695 (link available 2015.05)

  10. http://www.maximintegrated.com/en/app-notes/index.mvp/id/283

    Maxim Integrated Products, Inc., TUTORIAL 283: INL/DNL Measurements for High-Speed Analog-to-Digital Converters (ADCs) (link available 2015.05)

  11. http://www.maximintegrated.com/en/app-notes/index.mvp/id/1023

    Maxim Integrated Products, Inc., TUTORIAL 1023: Understanding Pipelined ADCs (link available 2015.05)

  12. http://www.maximintegrated.com/en/app-notes/index.mvp/id/1870

    Maxim Integrated Products, Inc., TUTORIAL 1870: Demystifying Delta-Sigma ADCs (link available 2015.06)