Tags: ADC, analog to digital converter, cmos, delta-sigma, education, oversampling, PDM, pulse density modulation, sigma-delta, theory



          “The Summary” section presents the architecture of the delta-sigma ADC with its advantages and disadvantages listed. “The Story” section explains the delta-sigma architecture and its working principles. The first-order delta-sigma architecture and its exemplary implementation are presented and explained. Analog and digital parts of the architecture are pointed out. A lot of expressions such as Pulse Density Modulation (PDM), oversampling and noise shaping are described. Higher orders of the delta-sigma architecture are briefly discussed.

          “The Story” sections consists of following chapters:

  • Introduction

  • How it works?

  • Oversampling

  • Digital part of delta-sigma

  • Higher orders of delta-sigma

  • Conclusion





delta-sigma - 1st order

Figure 32: The first-order delta-sigma ADC.



  • highest resolution possible [7]

    • 12- to 24-bits [7]

    • the resolution better than many SAR converters [8]

  • potentially capable to achieve hundreds of MSPS at 6- to 8-bit resolution [7]

  • low cost

  • reduced circuit complexity

  • low power consumption

  • averages input signal (noise cancellation) in the same manner as an integrating ADC [8]



  • the increase in number of bits results in linear increase of the die size [7]

  • applications:

    • the tool of choice for audio digitization for computers, for inexpensive high-resolution digitizers, and for digital signal processors that need not digitize at high speeds [8]

    • converters, frequency synthesizers, switched-mode power supplies and motor controllers [5]

    • strong position in the data-converter market [6]

    • process control, precision temperature measurements, and weighing scales [12]

  • architecture (for 1st order delta-sigma):

    • subtractor

    • integrator

    • comparator

    • 1-bit DAC

    • digital:

      • digital filter

      • decimation block

  • sources of accuracy errors (1st order delta-sigma in Fig. 34):

    • reference voltage VREF

    • pulse width Ttimer

    • opamp:

      • offset voltage



  • slow:

    • bandwidth of the input signal is typically less than 1 MHz [7]





1. Introduction

          The first-order delta-sigma, called also sigma-delta or oversampling ADC, is presented in Fig. 33.


delta-sigma - 1st order analog part

Figure 33: The first-order delta-sigma ADC.


          The input signal voltage VIN and 1-bit DAC output voltage VDAC are subtracted and the resulting voltage Vsubtractor is processed by the integrator. The integrator output voltage Vintegrator is compared by the latched comparator to the reference voltage – here the ground. The result of the comparison, the output voltage VOUT, is either a logic “1” or logic “0”. If VOUT is equal to “1”, it is latched for a set known period of time T. The working principle of the delta-sigma converter is a little bit sophisticated at the first glance, thus the reader is encouraged to continue the reading not worrying that some parts may not be understandable yet. After the second reading almost everything in this text should be clear.

          The output of the sigma-delta converter is either power supply or ground, or in other words logic “1” or logic “0”. The number of logic ones (pulses) is proportional to the value of the analog input signal VIN. Hence, delta-sigma converter is a voltage to frequency converter. The output is the pulse density modulation or PDM (not PWM which stands for pulse width modulation).

          Let’s look how the delta-sigma works.


2. How it works?

          The example of implementation of the first-order sigma-delta is presented in Fig. 34:


delta-sigma - 1st order impelmentation

Figure 34: Example of implementation of the first-order delta-sigma ADC [2].


          The negative reference voltage -VREF is two times greater than the maximum value of the input voltage VIN_MAX.

          The delta-sigma works in two phases.

          During the phase 1, the switch S1 is closed for the time equal to Ttimer. VOUT is equal to “1”. The currents I1, I2 and I3 are equal to:


currents equation


          The current I2 charges the C1 capacitor, hence the integrator output voltage V1 rises linearly as:




          The phase 2 starts after the time Ttimer. The VOUT voltage changes from “1” to “0”. During phase 2, the switch S1 is opened. Now, I2 current is equal to:


and the voltage V1 drops linearly as:



until it achieves 0 V – the level set by the voltage applied to the positive input of the comparator, here the ground. ∆V1 is a known value. It is equal to the voltage value that C1 was charged during Ttimer – see Eq. 4. Thus ∆t, can be calculated as:




          When V1 drops to 0 V, the comparator output voltage Vcomparator changes from “0” to “1”. This is the signal for the timer to produce a pulse again. VOUT voltage is set high for the time equal to Ttimer and the whole conversion is repeated again and again.


          The conversion time tc is equal to:


          Similarly to the dual-slope integrating ADC, the conversion time tc is independent of R1 and C1 values – see Eq. 5 and 6.

          Accuracy of the conversion time tc and consequently the output pulse frequency fOUT depends primarily on the negative reference voltage value -VREF and the pulse width Ttimer – see Eq. 5 And 6. However, a reference voltage value can be controlled nicely (for example bandgap references can be used), while the specific time period can be obtained from a crystal-controlled clock [2].

          The conversion time tc is proportional to the input signal value VIN – see Eq. 5 and 6 and Table 5. Remember that the maximum VIN voltage can be equal to |VREF| / 2.


Table 5: Dependence of the conversion time tc and the output pulse frequency fOUT on the input voltage value VIN for the delta-sigma in Fig. 34.

delta-sigma - table 1


          The maximum output frequency fOUT is equal to 1/2 ftimer (see Table 5) where ftimer is equal to:




          Maximum output frequency fOUT is set (remember that Ttimer is controlled by us) using the following equation [2]:




where 2 fIN stands for the Nyquist rate and N is the desired number of bits (the resolution of the converter). For example, to convert 10 kHz signal with 10-bit resolution fmax should be equal to:




          As a result, ftimer and Ttimer are equal to:




          The advantage of the sigma-delta architecture is the fact that the sampling noise is centered around a high clock frequency compared to the input signal frequencies. Moreover, the output signal pulses can be directly used by digital signal processing (DSP).

          In a conventional ADC, the analog input value is converted into a digital value. In a delta-sigma, the change in the signal value, its delta, is converted into a digital value which is a stream of pulses – pulse density modulation (PDM). “Sigma” stands for the summation that is performed by the integrator.

          The analog part of the delta-sigma ADC is very simple, thus the ADC is cheap. A lot of signal processing can be done in the digital part of the converter once a stream of pulses, that represent an analog signal, exists. The digital part performs filtering and decimation.



3. Oversampling

          Delta-sigma converters are called oversampling converters due to the fact that they sample the input signal using much higher frequencies than the Nyquist rate. The Nyquist rate is two times greater than the input signal maximum frequency. The higher the sampling frequency, the noise energy is spread across the wider frequency range. The signal-to-noise ratio (SNR) does not change yet. However, when the filter is used, some of the noise energy can be cut off and the SNR can be improved. See Figures 1, 2 and 3 on:



          SNR is calculated as [12]:


SNR  =  6.02 N  +  1.76 dB


          Thus, 1-bit ADC exhibit SNR equal to [12]:


6.02 dB  +  1.76 dB  =  7.78 dB


          Each oversampling by 4 increase the SNR by 6 dB [12], what is equal to increase of 1-bit in resolution, that is 6.02 dB – see Eq. 7. Thus, in order to achieve N-bit resolution using 1-bit ADC, the sampling frequency fsampling must be equal to:




where Nyquist frequency is two times greater than the maximum frequency in the input signal bandwidth:




          Table 6 summarizes what should be the value of the sampling frequency fsampling for 1-bit ADC in order to achieve a desired resolution.


Table 6: Table presents what should be the value of the sampling frequency fsampling for 1-bit ADC in order to achieve N-bit resolution.



          Thus, 1 kHz input signal should be sampled using 262.144 MHz in order to achieve “just” 10-bit resolution. But how it is possible that delta-sigma converters achieve much higher resolutions, from 12- to 24-bit resolution?

          The answer is: the delta-sigma converter not only oversamples the input signal, but due to its architecture it shapes the noise spectrum. “(…) the integrator acts as a lowpass filter to the input signal and a highpass filter to the quantization noise. Thus, most of the quantization noise is pushed into higher frequencies (…)” [12]. The total noise power is not changed, but the noise distribution changes [12]. See Figure 5 on:



          Now, more noise energy can be cut off by the same filter. Hence, SNR increases.

         Moreover, the higher the delta-sigma order, the better the noise shaping properties for a given oversampling ratio. See Table 7 and Figure 8 on:



Table 7: Noise shaping properties of a delta-sigma converter increases with its order.

delta-sigma order vs oversampling slope



4. Digital part of delta-sigma

          The output from the latched comparator is a 1-bit stream of pulses with varying density (pulse density modulation – PDM). This stream is processed by the digital part of the delta-sigma converter as seen in Fig. 35. The frequency of the stream can be very high, for example tens of MHz. The frequency of the output stream can be reduced without the loss of information to more friendly data rates and consequently the power consumption of the digital part of delta-sigma can be reduced. The frequency of the output stream is reduced in two steps. Firstly, the stream is filtered and secondly decimation procedure is applied.


delta-sigma - 1st order analog and digital parts

Figure 35: Analog and digital parts of 1st order delta-sigma ADC.


          The digital filter is used to prevent aliasing. Moreover it cuts off the noise shaped by the analog part of the delta-sigma converter. The SNR is improved. The cut-off frequency of the filter is two times greater than the new signal frequency that is obtained at the output of the decimation block. The information is not lost (see Figure 11 at [12]), but the signal has lower rates what improves power consumption.


5. Higher orders of delta-sigma

          The higher orders of the delta-sigma architecture called the second-order and third-order are available. Even the fourth- and fifth-order architectures have been constructed [4]. The higher the order, the more feedback loops in the design and the performance of the converter is improved. However, the higher the order, the less stable the converter is. The example of the 2nd order delta-sigma converter is presented in Fig. 36.


delta-sigma - 2nd order

Figure 36: Block schematic of the 2nd order sigma-delta ADC.



          The delta-sigma is very attractive architecture. It competes with almost every other architecture. The delta-sigma offers the highest resolution possible, low cost, low power consumption and noise shaping properties.



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  2. Camenzind H., Designing Analog Chips, February 2005

  3. Maloberti Franco, Data Converters, 2007, Springer

  4. Norsworthy S.R., Schreier R., Temes G.C., Delta-sigma Data Converters Theory, Design, and Simulation, 1997

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    Delta-sigma modulation (link available 2015.06)

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    Direct link to document: http://www.cypress.com/?docID=32695 (link available 2015.05)

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  11. http://www.maximintegrated.com/en/app-notes/index.mvp/id/1023

    Maxim Integrated Products, Inc., TUTORIAL 1023: Understanding Pipelined ADCs (link available 2015.05)

  12. http://www.maximintegrated.com/en/app-notes/index.mvp/id/1870

    Maxim Integrated Products, Inc., TUTORIAL 1870: Demystifying Delta-Sigma ADCs (link available 2015.06)