Tags: ADC, analog to digital converter, cmos, deltasigma, education, oversampling, PDM, pulse density modulation, sigmadelta, theory
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Abstract:
“The Summary” section presents the architecture of the deltasigma ADC with its advantages and disadvantages listed. “The Story” section explains the deltasigma architecture and its working principles. The firstorder deltasigma architecture and its exemplary implementation are presented and explained. Analog and digital parts of the architecture are pointed out. A lot of expressions such as Pulse Density Modulation (PDM), oversampling and noise shaping are described. Higher orders of the deltasigma architecture are briefly discussed.
“The Story” sections consists of following chapters:

Introduction

How it works?

Oversampling

Digital part of deltasigma

Higher orders of deltasigma

Conclusion
THE SUMMARY
Figure 32: The firstorder deltasigma ADC.
Advantages:

highest resolution possible [7]

12 to 24bits [7]

the resolution better than many SAR converters [8]


potentially capable to achieve hundreds of MSPS at 6 to 8bit resolution [7]

low cost

reduced circuit complexity

low power consumption

averages input signal (noise cancellation) in the same manner as an integrating ADC [8]
Remarks:

the increase in number of bits results in linear increase of the die size [7]

applications:

the tool of choice for audio digitization for computers, for inexpensive highresolution digitizers, and for digital signal processors that need not digitize at high speeds [8]

converters, frequency synthesizers, switchedmode power supplies and motor controllers [5]

strong position in the dataconverter market [6]

process control, precision temperature measurements, and weighing scales [12]


architecture (for 1^{st} order deltasigma):

subtractor

integrator

comparator

1bit DAC

digital:

digital filter

decimation block



sources of accuracy errors (1^{st} order deltasigma in Fig. 34):

reference voltage V_{REF}

pulse width T_{timer}

opamp:

offset voltage


Disadvantages:

slow:

bandwidth of the input signal is typically less than 1 MHz [7]

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THE STORY
1. Introduction
The firstorder deltasigma, called also sigmadelta or oversampling ADC, is presented in Fig. 33.
Figure 33: The firstorder deltasigma ADC.
The input signal voltage V_{IN} and 1bit DAC output voltage V_{DAC} are subtracted and the resulting voltage V_{subtractor} is processed by the integrator. The integrator output voltage V_{integrator} is compared by the latched comparator to the reference voltage – here the ground. The result of the comparison, the output voltage V_{OUT}, is either a logic “1” or logic “0”. If V_{OUT} is equal to “1”, it is latched for a set known period of time T. The working principle of the deltasigma converter is a little bit sophisticated at the first glance, thus the reader is encouraged to continue the reading not worrying that some parts may not be understandable yet. After the second reading almost everything in this text should be clear.
The output of the sigmadelta converter is either power supply or ground, or in other words logic “1” or logic “0”. The number of logic ones (pulses) is proportional to the value of the analog input signal V_{IN}. Hence, deltasigma converter is a voltage to frequency converter. The output is the pulse density modulation or PDM (not PWM which stands for pulse width modulation).
Let’s look how the deltasigma works.
2. How it works?
The example of implementation of the firstorder sigmadelta is presented in Fig. 34:
Figure 34: Example of implementation of the firstorder deltasigma ADC [2].
The negative reference voltage V_{REF} is two times greater than the maximum value of the input voltage V_{IN_MAX}.
The deltasigma works in two phases.
During the phase 1, the switch S_{1} is closed for the time equal to T_{timer}. V_{OUT} is equal to “1”. The currents I_{1}, I_{2} and I_{3} are equal to:
The current I_{2} charges the C_{1} capacitor, hence the integrator output voltage V_{1} rises linearly as:
The phase 2 starts after the time T_{timer}. The V_{OUT} voltage changes from “1” to “0”. During phase 2, the switch S_{1} is opened. Now, I_{2} current is equal to:
and the voltage V_{1} drops linearly as:
until it achieves 0 V – the level set by the voltage applied to the positive input of the comparator, here the ground. ∆V_{1} is a known value. It is equal to the voltage value that C_{1} was charged during T_{timer} – see Eq. 4. Thus ∆t, can be calculated as:
When V_{1} drops to 0 V, the comparator output voltage V_{comparator} changes from “0” to “1”. This is the signal for the timer to produce a pulse again. V_{OUT} voltage is set high for the time equal to T_{timer} and the whole conversion is repeated again and again.
The conversion time t_{c} is equal to:
Similarly to the dualslope integrating ADC, the conversion time t_{c} is independent of R_{1} and C_{1} values – see Eq. 5 and 6.
Accuracy of the conversion time t_{c} and consequently the output pulse frequency f_{OUT} depends primarily on the negative reference voltage value V_{REF} and the pulse width T_{timer} – see Eq. 5 And 6. However, a reference voltage value can be controlled nicely (for example bandgap references can be used), while the specific time period can be obtained from a crystalcontrolled clock [2].
The conversion time t_{c} is proportional to the input signal value V_{IN} – see Eq. 5 and 6 and Table 5. Remember that the maximum V_{IN} voltage can be equal to V_{REF} / 2.
Table 5: Dependence of the conversion time t_{c} and the output pulse frequency f_{OUT} on the input voltage value V_{IN} for the deltasigma in Fig. 34.
The maximum output frequency f_{OUT} is equal to 1/2 f_{timer} (see Table 5) where f_{timer} is equal to:
Maximum output frequency f_{OUT} is set (remember that T_{timer} is controlled by us) using the following equation [2]:
where 2 f_{IN} stands for the Nyquist rate and N is the desired number of bits (the resolution of the converter). For example, to convert 10 kHz signal with 10bit resolution f_{max} should be equal to:
As a result, f_{timer} and T_{timer} are equal to:
The advantage of the sigmadelta architecture is the fact that the sampling noise is centered around a high clock frequency compared to the input signal frequencies. Moreover, the output signal pulses can be directly used by digital signal processing (DSP).
In a conventional ADC, the analog input value is converted into a digital value. In a deltasigma, the change in the signal value, its delta, is converted into a digital value which is a stream of pulses – pulse density modulation (PDM). “Sigma” stands for the summation that is performed by the integrator.
The analog part of the deltasigma ADC is very simple, thus the ADC is cheap. A lot of signal processing can be done in the digital part of the converter once a stream of pulses, that represent an analog signal, exists. The digital part performs filtering and decimation.
3. Oversampling
Deltasigma converters are called oversampling converters due to the fact that they sample the input signal using much higher frequencies than the Nyquist rate. The Nyquist rate is two times greater than the input signal maximum frequency. The higher the sampling frequency, the noise energy is spread across the wider frequency range. The signaltonoise ratio (SNR) does not change yet. However, when the filter is used, some of the noise energy can be cut off and the SNR can be improved. See Figures 1, 2 and 3 on:
http://www.maximintegrated.com/en/appnotes/index.mvp/id/1870
SNR is calculated as [12]:
SNR = 6.02 N + 1.76 dB
Thus, 1bit ADC exhibit SNR equal to [12]:
6.02 dB + 1.76 dB = 7.78 dB
Each oversampling by 4 increase the SNR by 6 dB [12], what is equal to increase of 1bit in resolution, that is 6.02 dB – see Eq. 7. Thus, in order to achieve Nbit resolution using 1bit ADC, the sampling frequency f_{sampling} must be equal to:
where Nyquist frequency is two times greater than the maximum frequency in the input signal bandwidth:
Table 6 summarizes what should be the value of the sampling frequency f_{sampling} for 1bit ADC in order to achieve a desired resolution.
Table 6: Table presents what should be the value of the sampling frequency f_{sampling} for 1bit ADC in order to achieve Nbit resolution.
Thus, 1 kHz input signal should be sampled using 262.144 MHz in order to achieve “just” 10bit resolution. But how it is possible that deltasigma converters achieve much higher resolutions, from 12 to 24bit resolution?
The answer is: the deltasigma converter not only oversamples the input signal, but due to its architecture it shapes the noise spectrum. “(…) the integrator acts as a lowpass filter to the input signal and a highpass filter to the quantization noise. Thus, most of the quantization noise is pushed into higher frequencies (…)” [12]. The total noise power is not changed, but the noise distribution changes [12]. See Figure 5 on:
http://www.maximintegrated.com/en/appnotes/index.mvp/id/1870
Now, more noise energy can be cut off by the same filter. Hence, SNR increases.
Moreover, the higher the deltasigma order, the better the noise shaping properties for a given oversampling ratio. See Table 7 and Figure 8 on:
http://www.maximintegrated.com/en/appnotes/index.mvp/id/1870
Table 7: Noise shaping properties of a deltasigma converter increases with its order.
4. Digital part of deltasigma
The output from the latched comparator is a 1bit stream of pulses with varying density (pulse density modulation – PDM). This stream is processed by the digital part of the deltasigma converter as seen in Fig. 35. The frequency of the stream can be very high, for example tens of MHz. The frequency of the output stream can be reduced without the loss of information to more friendly data rates and consequently the power consumption of the digital part of deltasigma can be reduced. The frequency of the output stream is reduced in two steps. Firstly, the stream is filtered and secondly decimation procedure is applied.
Figure 35: Analog and digital parts of 1^{st} order deltasigma ADC.
The digital filter is used to prevent aliasing. Moreover it cuts off the noise shaped by the analog part of the deltasigma converter. The SNR is improved. The cutoff frequency of the filter is two times greater than the new signal frequency that is obtained at the output of the decimation block. The information is not lost (see Figure 11 at [12]), but the signal has lower rates what improves power consumption.
5. Higher orders of deltasigma
The higher orders of the deltasigma architecture called the secondorder and thirdorder are available. Even the fourth and fifthorder architectures have been constructed [4]. The higher the order, the more feedback loops in the design and the performance of the converter is improved. However, the higher the order, the less stable the converter is. The example of the 2^{nd} order deltasigma converter is presented in Fig. 36.
Figure 36: Block schematic of the 2^{nd} order sigmadelta ADC.
Conclusion:
The deltasigma is very attractive architecture. It competes with almost every other architecture. The deltasigma offers the highest resolution possible, low cost, low power consumption and noise shaping properties.
References:

Baker R. Jacob, CMOS Circuit Design, Layout, and Simulation, 3^{rd} Edition, 2010, John Wiley & Sons

Norsworthy S.R., Schreier R., Temes G.C., Deltasigma Data Converters Theory, Design, and Simulation, 1997

http://en.wikipedia.org/wiki/Deltasigma_modulation
Deltasigma modulation (link available 2015.06)

http://pdfserv.maximintegrated.com/en/an/AN634.pdf
Maxim Integrated Products, Inc., TUTORIAL 634: Pipeline ADCs Come of Age, Nov 20, 2001 (link available 2015.06)

http://pdfserv.maximintegrated.com/en/an/TUT810.pdf
Maxim Integrated Products, Inc., TUTORIAL 810: UNDERSTANDING FLASH ADCS, (link available 2015.05)

http://www.asdlib.org/onlineArticles/elabware/Scheeline_ADC/ADC_ADC.html#ADCMain
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http://www.cypress.com/?id=4&rID=32117
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Direct link to document: http://www.cypress.com/?docID=32695 (link available 2015.05)

http://www.maximintegrated.com/en/appnotes/index.mvp/id/283
Maxim Integrated Products, Inc., TUTORIAL 283: INL/DNL Measurements for HighSpeed AnalogtoDigital Converters (ADCs) (link available 2015.05)

http://www.maximintegrated.com/en/appnotes/index.mvp/id/1023
Maxim Integrated Products, Inc., TUTORIAL 1023: Understanding Pipelined ADCs (link available 2015.05)

http://www.maximintegrated.com/en/appnotes/index.mvp/id/1870
Maxim Integrated Products, Inc., TUTORIAL 1870: Demystifying DeltaSigma ADCs (link available 2015.06)